Computing and information and communications technology (ICT) has dramatically changed how we work and live, has had profound effects on nearly every sector of society, has transformed whole industries, and is a key component of U.S. global leadership. A fundamental driver of advances in computing and ICT has been the fact that the single-processor performance has, until recently, been steadily and dramatically increasing year over year, based on a combination of architectural techniques, semiconductor advances, and software improvements. Users, developers, and innovators were able to depend on those increases, translating that performance into numerous technological innovations and creating successive generations of ever more rich and diverse products, software services, and applications that had profound effects across all sectors of society.1 However, we can no longer depend on those extraordinary advances in single-processor performance continuing.
This slowdown in the growth of single-processor computing performance has its roots in fundamental physics and engineering constraints—multiple technological barriers have converged to pose deep research challenges, and the consequences of this shift are deep and profound for computing and for the sectors of the economy that depend on and assume, implicitly or explicitly, ever-increasing performance. From a technology standpoint, these challenges have led to heterogeneous multicore chips and a shift to alternate innovation axes that include, but are not limited to, improving chip performance, mobile devices, and cloud services. As these technical shifts reshape the computing industry, with global consequences, the United States must be prepared to exploit new opportunities and to deal with technical challenges. The following sections outline the technical challenges, describe the global research landscape, and explore implications for competition and national security.
Sequential Past, Parallel Future
For multiple decades, single-processor performance has increased exponentially, driven by higher clock rates, reductions in transistor size, faster switching via fabrication improvements, and architectural and software innovations that increased performance while preserving software compatibility with previous-generation processors. This practical manifestation of Moore’s Law—the doubling of the number of transistors on a given amount of chip area every 18 to 24 months—created a virtuous cycle of ever-improving single-processor performance and enhanced software functionality.
Hardware and software capabilities and sophistication grew exponentially in part because hardware designers and software developers could innovate in isolation from each other, while still leveraging each other’s advances. Software developers created new and more feature-filled applications, confident that new hardware would deliver the requisite performance to execute those applications. In turn, chip designers delivered ever-higher performance chips, while maintaining compatibility with previous generations.
Users benefitted from this hardware-software interdependence in two ways. Not only would old
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1National Research Council, The Future of Computing: Game Over or Next Level?, Washington, D.C.: The National Academies Press (available online at http://www.nap.edu/catalog.php?record_id=12980) and NRC, 2003, Innovation in Information Technology, Washington, D.C.: The National Academies Press (available online at http://books.nap.edu/catalog.php?record_id=10795).
software execute faster on new hardware, without change, but also new applications exploited advances in graphics and rendering, digital signal processing and audio, networking and communications, cryptography and security—all made possible by hardware advances. Unfortunately, single-processor performance is now increasing at much lower rates—a situation that is not expected to change in the foreseeable future.
The causes for the declining rates of chip hardware performance improvements begin with the limit on chip power consumption, which is proportional to the product of the chip clock frequency and the square of the chip operating voltage. As chip clock frequencies rose from megahertz to gigahertz, chip vendors improved fabrication processes and reduced chip operating voltages and, thus, power consumption.
However, it is no longer practical to increase performance via higher clock rates, due to power and heat dissipation constraints. These constraints are themselves manifestations of more fundamental challenges in materials science and semiconductor physics at increasingly small feature sizes. While the market for the highest performance server processor chips continues to grow, the market demand for phones, tablets, and netbooks has also increased emphasis on low-power, energy-efficient processors that maximize battery lifetime.
Finally, the use of additional transistors to preserve the sequential instruction execution model while accelerating instruction execution reached the point of diminishing returns. Indeed, most of the architectural ideas that were once found only in exotic supercomputers (e.g., deep pipelines, multiple instruction issue, out-of-order instruction logic, branch prediction, data and instruction prefetching) are commonplace within microprocessors.
The combination of these challenges—power limitations, diminishing architecture returns, and semiconductor physics challenges—drove a shift to multicore processors (i.e., placing multiple processors, sometimes of differing power or performance and function, on a single chip). By making parallelism visible to the software, this technological shift disrupted the cycle of sequential performance improvements and software evolution atop a standard hardware base.
Beginning with homogeneous multicore chips (i.e., multiple copies of the same processor core), design alternatives are evolving rapidly, driven by the twin constraints of energy efficiency and high performance. In addition, system-on-a-chip designs are combining heterogeneous hardware functions used in smartphones, tablets, and other devices. The result is a dizzying variety of parallel functionality on each chip. It is likely that even more heterogeneity will arise from expanded use of accelerators and reconfigurable logic for increased performance while simultaneously meeting power constraints.
Whether homogeneous or heterogeneous, these chips are dependent on parallel software for operation, for there is no known alternative to parallel programming for sustaining growth in computing performance. However, unlike in the sequential case, there is no universally accepted, compelling programming paradigm for parallel computing. Absent such programming models and tools, creating increasingly sophisticated applications that fully and effectively exploit parallel chips is difficult at best. Thus, there exists a great opportunity and need for renewed research on parallel algorithms and programming methodologies, recognizing that this is a challenge and long-studied problem. However, because multicore chips are dependent on parallel programming, it is prudent to continue such explorations.
Although further research in parallel programming models and tools may ameliorate this problem (e.g., via domain-specific languages, high-level libraries, and toolkits), 40 years of research in parallel computing suggests this outcome is by no means certain. When combined with the need for increasingly rapid development cycles to respond to changing demands and the rising importance of software security and resilience in an Internet-connected world, the programming challenges are daunting. In combination, the continued slowing of processor performance and the uncertainty of a parallel software future poses potential short- and long-term risks for U.S. national security and the U.S. economy. This report focuses on the competitive position of the U.S. semiconductor and software industries and their impact on U.S. national security in the new norm of parallel computing.
Global Competition and the Research Landscape
Because of this disruption to the computing ecosystem,2 major innovations in semiconductor processes, computer architecture, and parallel programming tools and techniques are all needed if we are to continue to deliver ever-greater application performance.
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2The advanced computing ecosystem refers not only to the benefits from and interdependencies between breakthroughs in academic and industry science and engineering research and commercialization success by national, multi-national and global companies, but also the underlying infrastructure (that includes components such as workforce; innovation models, e.g., centralist versus entrepreneurial; global knowledge networks; government leadership and investment; the interconnectedness of economies; and global markets) that underpin technological success.
In the past, the U.S. Department of Defense’s (DOD) uptake of U.S. computing technology research designed especially for it and now increasingly adapted from the fast-moving consumer market has resulted in a large U.S. advantage. In the future, the rate of change in the competitive position of the United States in computing technology will increasingly depend in part on other countries’ basic research capabilities and the types of research and development (R&D) policies they pursue, as well as the associated economic climate. Of course, many factors influence the range and type of policy options available in each region. Countries also differ in their levels of development and in their economic institutions, and pursue quite different approaches to innovation policy.
Historically, the United States has relied on market forces and the private sector to convert university research ideas, funded by the federal government, into marketable products. In contrast, the European Union and emerging economies such as China, Korea, and Taiwan rely much more on the government to define the strategic objectives and key parameters. For example, recent Chinese innovation policies have played an increasing role in strengthening its indigenous innovation capabilities. There is also evidence that China is transitioning toward economic outcome-driven science and technology programs focused on technologies of national strategic importance—many of which are advanced computing technologies. In contrast, Taiwan’s innovation policies are focused on moving its IT industries beyond the traditional “global factory” model. Thus, innovation polices emphasize low-cost and fast innovation by strengthening public and private partnerships that leverage domestic and global innovation networks.
Competitive Implications and National Security
In the committee’s view, the United States currently enjoys a technological advantage in many computing technologies. Nonetheless, this technological gap is narrowing as other countries, such as China, make a concerted effort to develop their own indigenous computing design and manufacturing capabilities and as design and fabrication of such technologies, as well as software development, are increasingly distributed globally.
Thus, it is important to take a long-term perspective on our approaches to computing innovation, technology uptake, and defense policy, for the United State’s global competitors certainly are. The principal future national security concerns for the United States related to anticipated computing shifts and limits on single-processor performance come not just from the threat to U.S. technological superiority, but also from changes to the nature and structure of the marketplace for computing and information technology. U.S. challenges include maintaining the integrity of the global supply chain for semiconductors, which is exacerbated by the convergence of civilian and defense technologies, as well as the rise of a new ecosystem of smart devices, based on licensable components and created by semiconductor design firms without fabrication capabilities.
Over time, the increasing presence and establishment of foreign markets that are larger, are potentially more lucrative, and have better long-term growth potential than in the United States and other developed countries could also have significant implications. Any shift in the global commercial center of gravity could lead to a shift in the global R&D center of gravity as international firms are required to locate in these markets if they are to remain competitive and to meet the requirements of government regulations in the target markets.
Shifting from policy to technology, the parallel programming challenges in delivering high performance on multicore chips are real and global, with no obvious technical solutions. Barring research breakthroughs, developing applications that exploit on-chip parallelism effectively (or vice versa, by developing approaches to on-chip parallelism that better support application needs) will remain an intellectually challenging task that is dependent on highly skilled software developers. When combined with the need for rapid application development, nimble response to shifting threats, and the ever-present desire for new features, equating competitive advantage in computing solely with single-processor performance (and associated application performance) may not be wise. Going forward, metrics such as system reliability, energy efficiency, security adaptability, and cost will inevitably become more salient. Power consumption is the major constraint on chip performance and device utility. Innovation in software, architecture, hardware, and other computing technologies will continue apace, but the primary axes of innovation are shifting, and organizations such as the U.S. DOD will need to adapt their computing and IT strategies accordingly.
