Productivity and Cyclicality in Semiconductors Trends, Implications, and Questions: Report of a Symposium (2004) / Chapter Skim
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International Technology Roadmaps: The U.S. Semiconductor Experience
International Technology Roadmaps: The U.S. Semiconductor Experience
Pages 135-150
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From page 135... ...
This productivity improvement is demonstrated clearly in the continual decrease in cost of semiconductor memory from the first introduction of 1,000-bit chips in around 1970 to today's production of 4- and 16-megabit dynamic random access memories (DRAMs) , and it is expected to continue well into the twenty-first century (see Figure 1)
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From page 136... ...
This work was the result of hundreds of scientists and engineers from universities, industry, and government working together to develop a set of industry requirements for silicon technology. The history of this roadmap process, the methods used to develop the National Technology Roadmap for Semiconductors, some of the overall requirements of the Roadmap, and finally, some sugges
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The first semiconductor technology roadmaps were developed by SEMATECH in 1987. Earlier technology predictions were developed by the National Academy of Sciences' Committee on Science and Public Policy (COSEPUP)
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The first "organizing" workshop was held in Monterey, California; it provided a global competitive overview and developed planning guidelines for additional technology roadmapping to reach a competitive technology position for U.S. semiconductor manufacturers by 1990-1993.
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139 Headcount 700 600 500 400 300 200 100 0 Q4 Q3 1993 Q2 Q1 Q4 Q3 1992 mµ Q2 Q1 0.35 Q4 Q3 1991 Q2 mµ Q1 Q4 0.50 Q3 1990 Q2 mµ Plan. Q1 Q4 0.80 Q3 Operational 1989 Q2 Q1 Five-Year Q4 Q3 1988 Q2 Q1 SEMATECH 2 0 80 70 60 50 40 30 20 10 Dollars)
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The objectives of the workshop were "to determine if the MicroTech 2000 technical goal of developing a competitive 0.12 micron semiconductor manufacturing process ahead of current forecasts is feasible, to identify the most critical efforts that should be undertaken to develop the manufactur 5National Advisory Committee on Semiconductors, A Strategic Industry At Risk, Washington, D.C.: National Advisory Committee on Semiconductors, 1989; National Advisory Committee on Semiconductors, Preserving the Vital Base: America's Semiconductor Materials and Equipment Industry, Washington, D.C.: National Advisory Committee on Semiconductors, 1990; National Advisory Committee on Semiconductors, Capital Investment in Semiconductors: The Lifeblood of the U.S. Semiconductor Industry, Washington, D.C.: National Advisory Committee on Semiconductors, 1990; National Advisory Committee on Semiconductors, Toward a National Semiconductor Strategy, vols.
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0.35 0.25 0.18 On-chip SRAM 8Mb 64Mb 256Mb xx ing process and to produce engineering samples of a product using the process, and to determine when resources would have to be made available to reach the goal by the year 2000." The outcome of the workshop was a report to the full NACS in August 1991.6 The workshop met its goal of developing a technology roadmap that would advance semiconductor technology by roughly one generation by the year 2000. This would make possible the manufacture of a 1-Gigabit static random access memory (SRAM)
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This workshop consisted of 11 Technical Working Groups (TWGs) : Chip Design & Test, chaired by Richard Howard; Process Integration, chaired by Dirk Bartelink; Lithography, chaired by Gordon McMillan; Interconnect, chaired by Thomas Seidel; Materials & Bulk Processes, chaired by Dyer Matlock; Environment, Safety & Health, chaired by Phyllis Pei; Manufacturing Systems, chaired by Hal Bogardus; Manufacturing Facilities, chaired by Craig Schackleton; Process Device Structure/CAD, chaired by Don Scharfetter; Packaging, chaired by John Kelly; and Equipment Modeling & Design, chaired by Edward Hall.
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In this table, the progression of feature sizes and chip complexity follows historical trends. Entries are organized by date of introduction of production startup; however, some entries reflect attributes of each technology generation at maturity.
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7Semiconductor Industry Association, Semiconductor Technology Workshop Conclusions, San Jose, CA: Semiconductor Industry Association, 1993. 8Semiconductor Industry Association, Semiconductor Technology Workshop Working Group Reports, San Jose, CA: Semiconductor Industry Association, 1993.
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The key summaries from each TWG are abstracted here: · Design & Test is dealing with an increase in complexity that threatens the ability to economically manage the design of higher complexity. · Process Integration & Device Structure is faced with power, performance, signal integrity, and complexity issues that require lower voltage, process simplification, and cross-functional coordination.
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The Roadmap results 10Semiconductor Industry Association, The National Technology Roadmap for Semiconductors, San Jose, CA: Semiconductor Industry Association, 1994.
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In fact, SEMATECH's programs today are managed in an organization that reflects the technologies outlined in the National Technology Roadmap. The roadmapping process was not unique to the semiconductor industry.
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REFERENCES 1993 International Electron Device Meeting Technical Digest. Piscataway, NJ: WEE.
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1993. Semiconductor Technology Workshop Conclusions.
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